Generally, a tunneling field effect transistor (FET) is a device where drive current is dominated by inter-band tunneling and comprises a tunneling junction. Gated PIN diodes (e.g., tunnel FETs) have been shown to have similar tunneling device characteristics where current-voltage characteristics can be controlled by applying bias to the terminals of the device. These tunneling determined current-voltage characteristics enable a sub-threshold swing (e.g., gate voltage swing needed to increase the drain current by one decade (10×)) to not be limited to a thermal limit of 60 mV/dec, such as for conventional metal-oxide-semiconductor field-effect transistors (MOSFETs), for example. Accordingly, the sub-threshold swing in tunnel FETs are thus scalable. Various methods of fabrication have been proposed for tunnel FETs, such as different device designs. For example, a point tunneling FET generally comprises a tunneling region where tunneling occurs parallel to the gate. Thus, vertical and horizontal architectures have been proposed to enhance the tunneling probability. However, as tunneling occurs parallel to the gate, the tunneling direction is not aligned to the gate electric field. Hence, the tunneling efficiency is not efficient. Additionally, the sub-threshold swing of the point tunneling FET degrades as a function of gate bias. This degradation is undesirable as it limits VDD scaling and also the drive current and effective swing needed to turn on the devices. Line tunneling FET on the other hand, has been proposed such that tunneling occurs perpendicular to the gate and a tunneling direction is aligned to the gate electric field. However, such structures are made on homogeneous materials, and require heavily doped tunneling regions. To this end, a planar line tunneling FET is generally difficult to manufacture. Further, planar line tunneling devices require large gate-source overlap regions in order to have significant tunneling and are therefore non-scalable with respect to area required on the chip. Further, these devices also require stringent doping and/or geometry requirements at least due to the heavily doped tunneling region, for example. Accordingly, a device length and/or a gate length associated with a planar line tunneling FET generally is not scalable at least because the heavily doped region must lie on top of a source region and under a gate region. For example, in some FETs, a gate region must overlap at least a portion of the source region. Additionally, at least some current drifts from a channel of the FET to a drain of the FET, rather than tunneling, as desired. Issues arising from forming ultra-thin layers and/or tunneling regions, sharp tunneling junctions, heavy doping, and/or non-self aligning structures thus complicate fabrication associated with planar line tunneling FETs with doped junctions.